VIA Technologies Mini-ITX Manual do Utilizador descarregar pdf (Página 43)

Chapter 3

3-12

DRAM Clock/Drive Control

Press <Enter> to enter the sub-menu and the following screen appears:

DRAM Clock

Set the DRAM Clock. Settings: Host CLK, HCLK-33M and By Auto.

DRAM Timing By SPD

Set DRAM Timing by SPD. Settings: Disabled and Enabled.

SDRAM Cycle Length

Set the SDRAM Cycle Length. Settings: 3 and 2.

Bank Interleave

Set the Bank Interleave mode. Settings: Disabled, 2 Bank and 4

Bank.

1 2 ... 38 39 40 41 42 43 44 45 46 47 48 ... 107 108

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VIA Technologies Mini-ITX Manual do Utilizador Página 43